Synopsys Design Compiler Tutorial 2021 Now

Startpoint: reg_data_out_reg (rising edge-triggered flip-flop clocked by sys_clk) Endpoint: out_data[0] (output port clocked by sys_clk) Path Group: sys_clk Path Type: max Point Incr Path --------------------------------------------------------------- clock sys_clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 reg_data_out_reg/CLK (DFFX1) 0.00 0.00 r reg_data_out_reg/Q (DFFX1) 0.32 0.32 f U124/Y (AND2X2) 0.15 0.47 f U135/Y (OR2X1) 0.22 0.69 r out_data[0] (out) 0.11 0.80 r data arrival time 0.80 clock sys_clk (rise edge) 2.00 2.00 clock network delay (ideal) 0.00 2.00 clock uncertainty -0.15 1.85 output delay -0.40 1.45 data required time 1.45 --------------------------------------------------------------- data required time 1.45 data arrival time -0.80 --------------------------------------------------------------- slack (MET) 0.65 Use code with caution. Key Elements to Analyze:

With your setup ready, you can launch Design Compiler in its shell mode. There are two primary ways:

# Define paths set TECH_LIB "/path/to/tech_lib/tsmc_28nm" set SEARCH_PATH [list "." $TECH_LIB/synopsys] synopsys design compiler tutorial 2021

Design Compiler: Timing, Area, Power, & Test Optimization | Synopsys

This is the initialization file. DC looks for it in three locations in order: DC looks for it in three locations in

# Analyze SystemVerilog files analyze -format sverilog top_module.sv controller.sv datapath.sv # Elaborate the top-level design module elaborate top_module Use code with caution. Method B: Read File

Registering the outputs of your sub-modules simplifies timing budgeting. It makes input and output delays predictable across chip boundaries. set_output_delay -max 0

set_output_delay -max 0.8 -clock clk [all_outputs]

You can read files using either the read_file command or the safer, industry-preferred analyze and elaborate combination.

Before launching Design Compiler, create a local setup file named .synopsys_dc.setup inside your work/ directory. This file initializes the tool variables automatically upon startup.

Design Compiler can be operated in three different modes depending on your workflow requirements: